In typical computer-related devices, there is often a flash memory that involves a NAND-based architecture. The NAND-based architecture typically comprises one or more flash memory chips, a memory controller for executing flash translation code (FTL) code in Read-Only Memory (ROM), a Static Read-Access Memory (SRAM) for maintaining the address mapping information, and a host interface for communicating, such as that of a Personal Computer Memory Card International Association (PCMCIA) for example. In operation, a flash memory device is able to issue commands in association with logical sector addresses of and data resident on the flash device. Within the architecture of the device, commands of read, write, program and/or erase in relation to physical locations, or sector addresses, of the data (i.e., operational commands) are performed via the FTL.
Flash memory is a popular type of non-volatile computer storage chip having a NAND-based architecture. Memories having NAND-based architectures are typically found in memory cards, Universal Serial Bus (USB) flash drives, solid-state drives, and similar products, for general storage and transfer of data. NAND flash memory is also often used to store configuration data in numerous digital products. Example device applications of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, solid state storage, video games, scientific instrumentation, industrial robotics, routers, communication devices, programmable devices, medical electronics, and so on. Flash memory is popular in applications for consumers because of the robustness of the devices (i.e., shock and water resistance versus disc drives) as well as since flash memory offers fast read access times, as Its mechanical shock resistance helps explain its popularity over hard disks in portable devices; consequently, consumers often expect long-term performance from such devices and are often unfamiliar with the flash endurance limits and disturbance issues that may arise.
Typically, a flash memory drive is used to provide non-volatile storage to computer-based systems (such as a PC) by connection via a Universal Serial Bus (USB) or other bus. NAND is a common type of flash memory. Flash memory may be electrically erased and reprogrammed. Typically, the NAND-based architecture flash memory is programmed to read and be written to in blocks, or pages, where it may be the entirety of the block that is erased when new data is written to the block. In NAND memory (also used herein as “flash memory”), it is understood that before data can be programmed (or written to) a page, typically the page needs to have been erased or be otherwise available for writing. As a result fairly large blocks of data are often erased before new data can be written or rewritten to the page. It is further understood that within data there may be errors in content resulting from, but not limited to, data bits being flipped (ones are exchanged for zeroes, or vice versa), data being inaccurate, or some data being invalid.
Further, the inherent reliability of flash data may often be affected by a number of factors including: read disturbs, program disturbs, endurance, etc. In some instances bad block management (BBM), wear leveling (WL), and error correction efforts (such as error correction checking [ECC]) are engaged to assist in checking for errors after writing to a page.
BBM is required as bad blocks may result during usage following erase fails, program fails, and read fails. WL is required as a result of each block within a NAND flash having a limited life (i.e., erase count or endurance limit); by example, though a Single-Level Cell (SLC) flash may typically outperform a Multi-Level Cell (MLC) flash by being faster from using a simpler control logic with 1 bit versus the 2 bits used by MLC flash, the lifespan (i.e. endurance) of the SLC chip is often rated at ten times that of the MLC chip's rating of 10 k write/erase cycles per cell. Similarly, while ECC, in various competencies, is often used to detect and correct the presence of errors to reconstruct the original, error-free data within certain limits, errors may still result even with address correction logic present and often strict error correction approaches may require additional time which thereby further constrains performance.
For instance, in traditional operating systems, software is often a means for determining whether a page has been written to or not and therefore whether the page is available for being written to or not with new data. Operationally, for a typical 4 kB page, the software will read from the flash device and then store a target page in a temporary location. Thereafter, a count of the number of ones (i.e., data bits having the value “1”) resident on the page is performed, where if the cumulative total of data indicates ones totaling 4 kB, then the software can determine that the page is available for writing as the page has been erased of prior data or similar. Contradistinctively, if the cumulative total of data indicates ones totaling less than 4 kB, then the software may conclude that the page is not available for writing as the page has not been erased of prior data or similar even though the page may have been erased, as the discrepancy may have arisen from errors associated with the flash data (i.e., read disturbance, etc.). This approach, and particularly those that may read a byte at a time, are understood and recognized to be time-intensive processes resulting in overall performance impacts that are not desirable.
Similarly, it is understood that a hardware-based approach may also involve reading a page for the presence of data having ones, where if the number of ones on a page is equal to the number of bits sought for the page, an indication that the page has been erased is set forth. In contrast, if the number of ones on a page is not equal to the number of bits sought for the page, an indication that the page has not been erased is determined. This approach often involves reading a byte at a time with reduced performance that are not desirable.
However, since flash devices are inherently erroneous and subject to read disturbances, bits may be flipped more often than is desired such that the approaches in software or in hardware are too time-intensive to implement. Though both prior approaches seek a similar outcome, each may yield a determination that the data of a target page has not been erased when it actually has been, simply because certain data bits of one were flipped to zero. Other attempts may also then seek to have a controller having error correction logic that is able to check the validity of the page. Unfortunately, even after data is written to a flash with error correction (such that when the data of the page is read back that data can be corrected when in error because of the error correction), checking for the correctness or errors associated with the page data requires additional time-intensive processing.
Many of these prior approaches add additional overhead and further limit the utility of the system capacity.
As a result, it is desirable to mitigate the impact of errors and the need to seek additional time-intensive processing, particularly on a bit by bit basis, in order to determine the availability of page to have data written to it, preferably without having to undergo additional time-intensive processing steps.
Rather what is needed is a method and system to determine whether a target page of a particular device is available to be written to in relation to error performances associated with the particular device without having to undergo additional time-intensive processing steps or bit by bit data assessment of a target page.
As used herein the term “NAND-based architecture” is intended to include those architectures and techniques for memory devices, systems and peripherals which are organized into a plurality of blocks where each block comprises a plurality of pages and each page typically defines an individually addressable physical memory location. Further “NAND-based architectures” are also intended to include any memory architecture, including implementations, in which read disturbance(s) or disturbance events resulting from retrieval of data may occur.
FIG. 1 sets forth diagrammatic overview of a NAND-based array 100. From the example of FIG. 1, the array (100) has 1024 k pages (120) which are approximately 8192 blocks. A block, within the array has 128 pages, of 528 k bytes. In general, for such an exemplary array, 1 page typically has (4 k+128) bytes; each block has (4 k+128) bytes by 128 pages equivalent to (512 k+16 k) bytes; and each device has (4 k+128) bytes by 128 pages by 8192 blocks or approximately 33,792 Mbits of data.
Further from FIG. 1, a page register (140) has 4 k bytes (at 150) plus 128 bytes (at 160) for information such as error code storage and related detail. Each NAND page has sectors within the page.
As used herein the terms device, apparatus, system, etc. are intended to be inclusive, interchangeable, and/or synonymous with one another and other similar arrangements and equipment for purposes of the present invention though one will recognize that functionally each may have unique characteristics, functions and/or operations which may be specific to its individual capabilities and/or deployment.